Semiconductor structure with substantially straight contact profile

ABSTRACT

The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor structure with a substantially straight contact profile and methods of manufacture. The structure includes a block material comprising an upper oxidized layer at an interface with an insulating material; and an interconnect contact structure with a substantially straight profile through the oxidized layer of the block material.

FIELD OF THE INVENTION

The present disclosure relates to semiconductor structures and, moreparticularly, to a semiconductor structure with a substantially straightcontact profile and methods of manufacture.

BACKGROUND

Semiconductor devices include many different wiring layers. These wiringlayers are formed in interlevel dielectric material and may includewiring structures, interconnect contacts, passive devices and activedevices. The interconnect contacts are provided in different wiringlayers of the die to connect to the different structures, e.g.,different wiring structures, etc.

In manufacturing the semiconductor devices, an adhesion layer istypically formed at a bottom surface of the interlevel dielectricmaterial, e.g., bulk SiCOH materials, above a wiring structure. Theadhesion layer, though, has a different etch rate than the interleveldielectric material, resulting in a tapered via profile. In other words,as the etch rate is different for the interlevel dielectric material andthe adhesion layer, these materials will etch at a different rateresulting in a tapered profile within the adhesion layer. The taperedvia profile, in turn, leads to interconnect contacts with taperedprofiles. This tapered profile of the interconnect contacts leads toelectrical performance issues including void formation in the metalmaterial, e.g., copper, as well as and time-dependent gate oxidebreakdown (TDDB).

The etching of these different materials is also known to be difficultto control as it is not possible to measure the thickness of theadhesion layer, in line. And, different thicknesses of the adhesionlayer will generate different tapered via profiles.

SUMMARY

In an aspect of the disclosure, a structure comprises: a block materialcomprising an upper oxidized layer at an interface with an insulatingmaterial; and an interconnect contact structure with a substantiallystraight profile through the oxidized layer of the block material.

In an aspect of the disclosure, a structure comprises: a wiring layerformed in an insulator material; a block material comprising an uppersurface composed of oxidized material; an interlevel dielectric materialdirectly on the upper surface; and a contact extending to the wiringlayer, through the block material, oxidized material and the interleveldielectric material, the contact having a substantially straight profilewithin the oxidized material.

In an aspect of the disclosure, a method comprises: forming a blockingmaterial over a wiring structure; oxidizing the blocking material toform an upper oxidized layer; forming an interlevel dielectric materialover the oxidized layer; etching a via into the interlevel dielectricmaterial, the oxidized layer and the blocking material to expose thewiring structure, the via having a substantially straight via profilethrough the oxidized layer; and forming a contact within the via, thecontact having a substantially straight profile through the oxidizedlayer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is described in the detailed description whichfollows, in reference to the noted plurality of drawings by way ofnon-limiting examples of exemplary embodiments of the presentdisclosure.

FIG. 1 shows a structure and respective fabrication processes inaccordance with aspects of the present disclosure.

FIG. 2 shows a via with a substantially straight profile, amongst otherfeatures, and respective fabrication processes in accordance withaspects of the present disclosure.

FIG. 3 shows an interconnect contact with a substantially straightprofile, amongst other features, and respective fabrication processes inaccordance with aspects of the present disclosure.

DETAILED DESCRIPTION

The present disclosure relates to semiconductor structures and, moreparticularly, to a semiconductor structure with a substantially straightcontact profile and methods of manufacture. More specifically, thepresent disclosure provides a substantially straight or verticalinterconnect contact profile within an oxidized film in a blockinglayer, below an interlevel dielectric material. Advantageously, by usingthe oxidized film, the present disclosure provides a more controllablevia etching process, resulting in improved electrical parametric valuesof the interconnect contact, e.g., reduction in voids and time-dependentgate oxide breakdown (TDDB).

In embodiments, an oxygen treatment is provided to an upper surface of aBLoK layer, e.g., low-k dielectric insulator material. This oxygentreatment will improve taper control, e.g., etching, at the interfacebetween an interlevel dielectric material and the BLoK layer. That is,by providing the oxygen treatment an oxidized layer of the BLoK layerwill have a similar etch rate as the interlevel dielectric layer. Theresulting via profile will, in turn, have a straight or substantiallystraight profile at the interface between the two materials, e.g.,substantially 90 degrees as measured relative to the horizontaldielectric surface, as the oxidized layer and the interlevel dielectriclayer will have a similar etch rate. In addition, by implementing theprocesses described herein, it is possible to eliminate the adhesionlayer formed at the bottom of the interlevel dielectric layer thattypically causes a tapered via profile during the etching process.

The structure of the present disclosure can be manufactured in a numberof ways using a number of different tools. In general, though, themethodologies and tools are used to form structures with dimensions inthe micrometer and nanometer scale. The methodologies, i.e.,technologies, employed to manufacture the structure of the presentdisclosure have been adopted from integrated circuit (IC) technology.For example, the structure can be built on wafers and are realized infilms of material patterned by photolithographic processes on the top ofa wafer. In particular, the fabrication of the structure uses threebasic building blocks: (i) deposition of thin films of material on asubstrate, (ii) applying a patterned mask on top of the films byphotolithographic imaging, and (iii) etching the films selectively tothe mask.

FIG. 1 shows a structure and respective fabrication processes inaccordance with aspects of the present disclosure. Specifically, thestructure 10 includes a wiring structure 12 formed in an insulatormaterial 14. In embodiments, the insulator material 14 can be an oxidebased material. The metal wiring structure 12 can be formed of a coppermaterial, for example, using conventional lithography, etching anddeposition processes.

For example, to form the wiring structure 12, a resist formed over theinsulator material 14 is exposed to energy (light) to form a pattern(opening). An etching process with a selective chemistry, e.g., reactiveion etching (RIE), will be used to form one or more trenches in theinsulator material 14 through the openings of the resist. The resist canthen be removed by a conventional oxygen ashing process or other knownstripants. Following the resist removal, the conductive material can bedeposited by any conventional deposition processes, e.g., electroplatingprocesses. Any residual material on the surface of the insulatormaterial 14 can be removed by conventional chemical mechanical polishing(CMP) processes.

Still referring to FIG. 1, a block material 16 is formed over theinsulator material 14 and the wiring structure 12. In embodiments, theblock material 16 is a low-k dielectric layer e, g., nitride material.In more specific embodiments, the block material 16 can be an NBLoK(NBLoK is a trademark of Applied Materials, Inc.), which is anitrogen-doped silicon carbide material. In embodiments, the blockmaterial 16 can be deposited by any conventional deposition process,e.g., chemical vapor deposition (CVD) processes, to a particularthickness depending on the technology node. By way non-limiting example,the thickness of the block layer and the thickness of the oxidized layershould be balanced such that the remaining block thickness is stillsufficient to act as diffusion barrier.

In embodiments, the block material 16 undergoes an oxygen treatment toform an oxidized layer 18. In embodiments, the oxidized layer 18 can beat an upper surface of the block material and, more specifically, canextend about 5 nm to about 25 nm, depending on the technology node;although other thicknesses are also provided herein. In more specificexamples, the oxidized layer 18 can be about 20% to about 30% of thethickness of the block material 16. In one specific embodiment, theoxidized layer 18 can be about 5 nm for a 35 nm thick block material 16.

The oxygen treatment can be provided in an oxygen atmosphere. The oxygenatmosphere can be, e.g., O₂, NO₂ or CO₂, in a carrier gas in a CVDchamber. For example, the oxygen treatment can be provided after thestart of the deposition process using the same CVD chamber as thedeposition process. For example, the oxidation treatment can be providedafter the start of or at the end of the deposition process of the blockmaterial 16. In this way, the oxidation can be provided in situ.Alternatively, the oxygen treatment can be provided prior to thedeposition interlevel dielectric material, e.g., oxygen pre-treatmentbefore SiCOH deposition, in either an external tool or within thedeposition chamber. As an example, the oxygen treatment can be providedusing a remote plasma tool, after the deposition process. Inembodiments, the oxygen treatment should not affect the underlying metalfeatures, e.g., wiring structure 12.

Still referring to FIG. 1, an interlevel dielectric material 20 isdeposited over the block material 16 and, in more specific embodiments,the interlevel dielectric material 20 can be bulk SiCOH depositeddirectly on the oxidized layer 18 using a conventional blanketdeposition process, e.g., CVD. Accordingly, in this latterimplementation, the oxygen treatment process would occur prior to thedeposition of the interlevel dielectric material 20. In embodiments, theetch rate of the interlevel dielectric material 20 and the oxidizedlayer 18 is similar, as should be understood by those of skill in theart. A stack of hardmasks 22, 24 is deposited on the interleveldielectric material 20. In embodiments, the hardmask 22 is an ILDhardmask 22 and the hardmask 24 is a TiN hardmask, as examples.

FIG. 2 shows a via 26 formed within the structure of FIG. 1. Inembodiments, the via 26 can be formed by a conventional dual or singledamascene process, as should be understood by those of skill in the artsuch that no further explanation is required herein. As the etching rateof the interlevel dielectric material 20 and the oxidized layer 18 havea substantially same etch rate, the portion of the via formed within theoxidized layer 18 will have a substantially straight profile 28(regardless of the thickness of the oxidized layer). In embodiments, thesubstantially straight profile 28 is it means substantially 90 degreesas measured relative to the horizontal surface of the dielectricmaterial or underlying wiring structure 12. The etching process can beperformed using conventional etching cycles, e.g., RIE processes, withthe interlevel dielectric material 20 and the oxidized layer 18, amongstthe other layers, being etched together, to expose the underlying wiringstructure 12.

FIG. 3 shows an interconnect contact 30 with a substantially straightprofile, amongst other features, formed in the via 26. Prior to thedeposition of the interconnect material, the hardmasks can be removed byknown stripping processes. The interconnect contact 30 will be formedwithin the via by conventional deposition processes, followed by achemical mechanical polishing (CMP), as an example. In embodiments, thedeposition of tungsten can be a CVD process, the deposition of aluminumcan be a plasma vapor deposition (PVD) process and other metal or metalalloy materials can be deposited by an electroplating process. Thestraight profile is due to the fact that the interconnect material isdeposited within the via with the straight profile 28.

The method(s) as described above is used in the fabrication ofintegrated circuit chips. The resulting integrated circuit chips can bedistributed by the fabricator in raw wafer form (that is, as a singlewafer that has multiple unpackaged chips), as a bare die, or in apackaged form. In the latter case the chip is mounted in a single chippackage (such as a plastic carrier, with leads that are affixed to amotherboard or other higher level carrier) or in a multichip package(such as a ceramic carrier that has either or both surfaceinterconnections or buried interconnections). In any case the chip isthen integrated with other chips, discrete circuit elements, and/orother signal processing devices as part of either (a) an intermediateproduct, such as a motherboard, or (b) an end product. The end productcan be any product that includes integrated circuit chips, ranging fromtoys and other low-end applications to advanced computer products havinga display, a keyboard or other input device, and a central processor.

The descriptions of the various embodiments of the present disclosurehave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

1. A structure, comprising: a block material comprising an upperoxidized layer at an interface with an insulating material, theinsulating material and the oxidized layer having substantially a sameetching rate regardless of a thickness of the oxidized layer; and aninterconnect contact structure with a substantially straight profilethrough the oxidized layer of the block material, the interconnectcontact structure extending through the insulating material andcontacting an underlying wiring structure, wherein the substantiallystraight profile is substantially 90 degrees as measured relative to ahorizontal surface of the underlying wiring structure.
 2. (canceled) 3.The structure of claim 1, wherein the insulating material is adielectric material composed of SiCOH.
 4. The structure of claim 1,wherein the oxidized layer is about 20% to 30% of a thickness of theblock material.
 5. (canceled)
 6. (canceled)
 7. The structure of claim 1,wherein the block material is composed of nitride material.
 8. Thestructure of claim 1, wherein the block material is composed ofnitrogen-doped silicon carbide.
 9. The structure of claim 8, wherein theinsulating layer is bulk SiCOH.
 10. A structure comprising: a wiringlayer formed in an insulator material; a low-k dielectric block materialcomprising an upper surface composed of oxidized material; an interleveldielectric material directly on the upper surface, the interleveldielectric material and the oxidized material of the low-k dielectricblock material having substantially a same etching rate regardless of athickness of the oxidized material; and a contact extending to thewiring layer, through the block material, oxidized material and theinterlevel dielectric material, the contact having a substantiallystraight profile within the oxidized material, the contact structureextending through the interlevel dielectric material and contacting thewiring layer, wherein the substantially straight profile issubstantially 90 degrees as measured relative to a horizontal surface ofthe wiring layer.
 11. The structure of claim 10, wherein the interleveldielectric material is composed of bulk SiCOH.
 12. The structure ofclaim 10, wherein the oxidized material is about 20% to 30% of athickness of the block material.
 13. The structure of claim 10, whereinthe interlevel dielectric material and the oxidized material havesubstantially a same etching rate.
 14. The structure of claim 13,wherein the low-k dielectric block material is composed of nitridematerial.
 15. The structure of claim 14, wherein the low-k dielectricblock material is composed of nitrogen-doped silicon carbide.
 16. Thestructure of claim 14, wherein the oxidized material has a thickness ofabout 12 nm to 25 nm. 17.-20. (canceled)
 21. The structure of claim 1,wherein the block material is a low-k dielectric material that coversinsulating material and partially covers an upper surface of theunderlying wiring structure.
 22. The structure of claim 21, wherein theinterconnect contact is tungsten and the insulating material is an oxidematerial.
 23. The structure of claim 22, wherein the underlying wiringstructure is a copper material.